Due to structural simplicity, DRAMs (dynamic random access to memories) can provide more memory cells per unit chip area than other types of memories such as static random access memories. A DRAM is constituted by a plurality of DRAM cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line is asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor to be read by a sense amplifier through a bit line. During a write operation, the data to be written is provided on the bit line while the word line is asserted.
To satisfy the demand for greater memory storage, DRAM memory cells need size reduction. DRAM memory cell size can be reduced in several ways. One way is to reduce the minimum feature size of a DRAM memory cell through the advances in process technology. Another way to reduce the size of a DRAM memory cell is by designing a memory cell having a smaller feature size. For example, many DRAM chips on the market today have a memory cell size of 6F2, where F stands for the photolithographic minimum feature width or critical dimension (CD).
However, as the size of memory cells decreases, a lot of issues emerge. For example, the disturbance between memory cells or between word lines may easily occur. The resistance of the word line increases due to the decrease of its cross-sectional area. In addition, the reduction of the areas of capacitors and bit line contacts increase the contact resistance.